A processor may include a plurality of Intellectual Property (IP) blocks. The term “IP block” generally refers to a logic cell or design which performs a certain function. An IP block may be a reusable unit of logic, cell, or chip layout design that is the Intellectual Property of a party. IP cores may be licensed to another party or can be owned and used by a single party alone. Examples of IP blocks include processor cores, caches, input-output (I/O) transceivers, etc.
In some low power operating modes, most of the IP blocks of the processor (or System-on-Chip (SoC)) may be powered down while the operating system may still consider the processor to be active and ready to continue processing instructions from the time point the processor entered the low power operating mode (or state). Since the operating system expects the hardware (i.e., the processor) to be ready, the entry and exit latency of low power operating mode(s) can significantly impact the performance of the computing system.
For example, the time it takes to save contents of registers in the processor so that the processor may enter a low power operating mode, and then the time to restore the registers back to their original states when the operating system desires the processor to process one or more instructions, constitutes the entry and exit latency of the low power operating mode. A higher latency means a slower response to operating system commands when the processor is in low power operating mode.